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Preliminary Technical Data
FEATURES
Wide bandwidth: 1 MHz to 10 GHz Dual-channel and channel difference outputs ports Integrated accurately scaled temperature sensor 50 dB dynamic range up to 8 GHz Stability over temperature 0.5 dB Low noise measurement/controller output VOUT Pulse response time: 8/10 ns (fall/rise) Small footprint 5 mm x 5 mm LFCSP package Supply operation: 3.0 V to 5.5 V @ 65 mA Fabricated using high speed SiGe process
1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller ADL5519
COMR COMR VPSA TEMP VPSR ADJA
24 23 22 21 20 19 18
CLPA
17
TEMP INHA 25 INLA 26 COMR 27 PWDN 28 COMR 29 CHANNEL A Log Detector
25 26 27 28
VSTA
NC OUTA FBKA OUTP OUTN FBKB OUTB NC
OUTA OUTB
29 30
APPLICATIONS
RF transmitter PA setpoint control and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLAN, WiMAX, radar Antenna VSWR monitor Dual-channel wireless infrastructure radios
COMR 30 INLB 31 INHB 32 BIAS
1 2 3 4 5 6 7 8
CHANNEL B Log Detector
31 32
COMR
COMR
GENERAL DESCRIPTION
The ADL5519 is a dual-demodulating logarithmic amplifier, using the AD8317 core. It has the capability of accurately converting an RF input signal to a corresponding decibel-scaled output. The ADL5519 provides accurately scaled, independent, logarithmic outputs of both RF measurement channels. Difference output ports, which measure the difference between the two channels, are also available. The on-chip channel matching makes the log-amp channel difference outputs extremely stable with temperature and process variations. The device also includes a useful temperature sensor with an accurately scaled voltage proportional to temperature, specified over the device operating temperature range. The ADL5519 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 50 dB (re: 50 ) with error less than 1 dB. The ADL5519 has 8/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current
Figure 1. Functional Block Diagram
consumption is typically 65 mA, and it decreases to 1 mA when the device is disabled. The device is capable of supplying four log-amp measurements simultaneously. Linear-in-dB measurements are provided at OUTA and OUTB, with conveniently scaled slopes of -22 mV/dB. The log-amp difference between OUTA and OUTB is available as differential or single-ended signals at OUTP and OUTN. An optional voltage applied to VLVL provides a common mode reference level to offset OUTP and OUTN above ground. On-chip wide bandwidth output op amps are connected to accommodate flexible configurations that support many system solutions. The ADL5519 can be easily configured to provide a control voltage to a power amplifier at any output pin. Since the output can be used for controller applications, special attention has been paid to minimize wideband noise The ADL5519 is fabricated on a SiGe bipolar IC process and is available in a 5 mm x 5 mm, 32-lead LFCSP package for an operating temperature range of -40oC to +125oC..
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
CLPB
VPSB
ADJB
VREF
VSTB
VLVL
ADL5519 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 13 Using the ADL5519 ........................................................................ 14 Basic Connections ...................................................................... 14 Input Signal Coupling................................................................ 14 Temperature Sensor Interface................................................... 14 Power-Down Interface............................................................... 15
Preliminary Technical Data
Setpoint Interface, VST[A, B] ................................................... 15 Output Interface, OUT[A, B] ................................................... 15 Difference Output, OUT[P, N]................................................. 15 Measurement Mode ................................................................... 16 Controller Mode......................................................................... 17 Temperature Compensation Adjustment................................ 20 Device Calibration and Error Calculation.............................. 20 Altering the Slope....................................................................... 21 Output Filtering.......................................................................... 21 Basis for Error Calculations ...................................................... 21 Evaluation Board ............................................................................ 23 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
Rev. PrB | Page 2 of 27
Preliminary Technical Data SPECIFICATIONS
VPOS = 5 V, CLPF = 1000 pF, TA = 25C, 52.3 termination resistor at INHI, unless otherwise noted. Table 1.
Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage MEASUREMENT MODE Conditions INH[A, B] (Pins 19. 24) 0.001 VPOS - 0.6 OUT[A, B] (Pins 12, 7) shorted to VST[A,B] (Pin 13, 6), OUT[P, N] (Pins 10, 9) shorted to FBK[A, B] [Pins 11, 8] respectively, sinusoidal input signal, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = +25C ADJA = ADJB = TBD to GND TBD TA = +25C -40C < TA < +85C -40C < TA < +125C OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm OUTP-OUTN Dynamic Gain Range Temperature Sensitivity 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation f = 900 MHz Input Impedance OUT[A, B] 1 dB Dynamic Range Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C 1 dB error 1 dB error TBD TBD TBD TBD TBD 50 46 TBD -3 -53 -22 15 0.58 1.27 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1 dB error 1 dB error TBD TBD TBD TBD 50 46 TBD -3 -53 -22 15 0.58 1.27 10 Min Typ
ADL5519
Max
Unit GHz V
f = 100 MHz Input Impedance OUT[A, B] 1 dB Dynamic Range
||pF dB dB dB dBm dBm TBD TBD TBD TBD mV/dB dBm V V dB dB dB dB dB dB dB dB dB dB dB ||pF dB dB dBm dBm mV/dB dBm V V
OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm
Rev. PrB | Page 3 of 27
TBD TBD TBD TBD
ADL5519
Parameter Temperature Sensitivity Conditions Deviation from OUT[A, B] @ 25C 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C 1 dB error 1 dB error
Preliminary Technical Data
Min .25 .25 .25 .5 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 950||0.38 50 48 TBD -4 -54 -22 14 0.54 1.21 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 50 47 TBD Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB ||pF dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB dB dB dB dB ||pF dB dB
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
.25 .25 .25 .5
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation f = 1.9 GHz Input Impedance OUT[A, B] 1 dB Dynamic Range
OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C
Rev. PrB | Page 4 of 27
TBD TBD TBD TBD .25 .25 .25 .5
TBD TBD TBD TBD
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
.25 .25 .25 .5
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation f = 2.2 GHz Input Impedance OUT[A, B] 1 dB Dynamic Range
Preliminary Technical Data
Parameter OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Conditions 1 dB error 1 dB error Min Typ -5 -55 -22 14 0.53 1.20 .25 .25 .25 .5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 42 40 TBD -6 -48 -22 11 0.47 1.16 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ADL5519
Max Unit dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB dB dB dB dB ||pF dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB dB dB
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range 25C < TA < 85C; PINH[A, B] = -10 to -15 dBm -20C < TA <25C; PINH[A, B] = -10 to -15 dBm 25C < TA < 85C; PINH[A, B] = -10 to -40 dBm -20C < TA <25C; PINH[A, B] = -10 to -40 dBm Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C 1 dB error 1 dB error
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
.25 .25 .25 .5
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation 1 f = 3.6 GHz Input Impedance OUT[A, B] 1 dB Dynamic Range
OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation 2
Rev. PrB | Page 5 of 27
ADL5519
Parameter f = 5.8 GHz Input Impedance OUT[A, B] 1 dB Dynamic Range Conditions ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C 1 dB error 1 dB error
Preliminary Technical Data
Min Typ TBD 50 48 TBD -4 -54 -22 16 0.59 1.27 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 44 Max Unit ||pF dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB dB dB ||pF dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB
OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB ADJA = ADJB = TBD to GND TA = +25C -40C < TA < +85C -40C < TA < +125C 1 dB error 1 dB error
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation 3 f = 8 GHz Input Impedance OUT[A, B] 1 dB Dynamic Range
OUT[A, B] Maximum Input Level OUT[A, B] Minimum Input Level OUT[A, B, P, N] Slope OUT[A, B] Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm 1 dB error -40C < TA < 85C OUTP-OUTN Dynamic Gain Range -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Freq separation = 1 kHz
Rev. PrB | Page 6 of 27
-2 -46 -22 21 0.7 1.39 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
OUTP-OUTN Dynamic Gain Range Temperature Sensitivity
Input A to Input B Isolation Input A to OUTB Isolation
Preliminary Technical Data
Parameter Input B to OUTA Isolation OUTPUT INTERFACE OUT[A, B] Voltage Range Min OUT[P, N] output OUT[P, N] Voltage Range Min Source/Sink Current Small Signal Bandwidth Output Noise Fall Time Fall Time Rise Time Rise Time Video Bandwidth (or Envelope Bandwidth) SETPOINT INTERFACE Nominal Input Range Logarithmic Scale Factor Logarithmic Intercept Input Resistance DIFFERENCE LEVEL ADJUST Voltage Range OUT[P, N] Voltage Range Input Impedance TEMPERATURE COMPENSATION Input Resistance Disable Threshold Voltage VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Current Limit Source/Sink TEMPERATURE REFERENCE Output Voltage Temperature Sensitivity Current Limit Source/Sink POWER-DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current Enable Time Conditions PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB OUT[A, B] (Pins 12, 7), OUT[P, N] (Pins 10, 9) VST[A, B] = TBD RFIN = open RL 240 to ground VST[A, B] = 0V RFIN = open RL 240 to ground OUT[A, B] = OUT[P, N] FBK[A, B] = TBD RFIN = open RL 240 to ground FBK[A, B] = 0V RFIN = open RL 240 to ground Output held at 1V to 1% change RFIN = -10 dBm, from CLP[A,B] to OUT[A,B] RF Input = 2.2 GHz, -10 dBm, fNOISE = 100 kHz, CLP[A,B] = open Input level = no signal to -10 dBm, 90% to 10%, CLP[A,B] = 8 pF Input level = no signal to -10 dBm, 90% to 10%, CLP[A,B] = open; Input level = -10 dBm to no signal, 10% to 90%, CLP[A, B] = 8 pF Input level = -10 dBm to no signal, 10% to 90%, CLP[A,B] = open, TBD TBD VLVL TBD TBD 2.2 TBD TBD TBD TBD TBD TBD 50 VST[A, B] (Pins 13, 6) Input level = 0 dBm, measurement mode Input level = -50 dBm, measurement mode Min Typ TBD TBD
ADL5519
Max Unit dB dB V V V V mA MHz nV/Hz ns ns ns ns MHz
Input level = -20 dBm, controller mode, VST[A,B] = 1 V VLVL (Pin 4) OUT[P, N] = FBK[A, B] OUT[P, N] = FBK[A, B] ADJ[A, B] (Pins 17, 2) ADJ[A, B] = 0.9 V, sourcing 50 A ADJ[A, B] = open VREF (Pin 3) -40C < TA < +85C TEMP (Pin 15) -40C < TA < +125C Pin PWDN Logic LO enables Logic HI disables Logic HI PWDN = 5 V Logic LO PWDN = 0 V PWDN LO to OUTA/OUTB at 100% final value, CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm
Rev. PrB | Page 7 of 27
0.5 1.75 -45 TBD 40
V V dB/V k
TBD TBD TBD 13 VPOS - 0.4 1.15 TBD 3/3 1.3 4.5 5/40 TBD TBD TBD TBD TBD
V V ||pF k V V mV/oC mA V mV/oC mA/uA V V A A s
ADL5519
Parameter Disable Time POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Disable Current Conditions PWDN HI to OUTA/OUTB at 10% final value, CLPA/B = Open, CHPA/B = 10nF, RF in = 0 dBm VPS[A, B, R] (Pins 18, 1, 16)
Preliminary Technical Data
Min Typ TBD Max Unit s
3.0 -40C TA +125C ADJ[A,B] = PWDN = VPOS 65 TBD 1
5.5
V mA A/C mA
Rev. PrB | Page 8 of 27
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage: VPSA, VPSB, VPSR VSET Voltage: VSTA, VSTB Input Power (Single-Ended, Re: 50 ) INHA, INLA, INHB, INLB Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.7 V 0 to VPOS 12 dBm
ADL5519
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
55C/W 165C -40C to +125C -65C to +150C 260C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 9 of 27
ADL5519 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
INHB INLB COMR COMR PWDN COMR INLA INHA
Preliminary Technical Data
COMR COMR VPSB ADJB VREF VLVL CLPB VSTB
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADL5519
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
COMR COMR VPSA ADJA VPSR TEMP CLPA VSTA
NC = NO CONNECT
NC OUTB FBKB OUTN OUTP FBKA OUTA NC
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name COMR COMR VPSB ADJB VREF VLVL CLPB VSTB NC OUTB FBKB OUTN OUTP FBKA OUTA NC VSTA CLPA TEMP VPSR ADJA VPSA COMR COMR INHA INLA COMR PWDN Description Common for difference output and Temp Sensor Common for difference output and Temp Sensor Positive Supply for Channel B. Must be the same as VPS[A/R]. Apply 3.0V to 5.5V supply voltage. Dual function pin. Channel B Temperature adjust. Connect a resistor to ground to vary temperature compensation. Connect to VPS[A/B/R] to power down Channel B. 1.15V voltage reference DC common mode adjust for difference output Loop filter pin for Channel B Setpoint Control input for Channel B No Connect Output voltage for Channel B Difference op-amp feedback pin Difference output (OUTB - OUTA + VLVL) Difference output (OUTA - OUTB + VLVL) Difference op-amp feedback pin Output voltage for Channel A No Connect Setpoint Control input for Channel A Loop filter pin for Channel A Temp Sensor output (1.3V with 4.5mV/oC slope) Positive Supply for difference output and temperature sensor. Must be the same as VPS[A/B]. Apply 3.0V to 5.5V supply voltage. Dual function pin. Channel A Temperature adjust. Connect a resistor to ground to vary temperature compensation. Connect to VPS[A/B/R] to power down Channel A. Positive Supply for Channel A. Must be the same as VPS[B/R]. Apply 3.0V to 5.5V supply voltage. Common for difference output and Temp Sensor Common for difference output and Temp Sensor AC coupled RF input for Channel A AC coupled RF common for Channel A Common for difference output and Temp Sensor Power down for difference output and Temp Sensor
Rev. PrB | Page 10 of 27
9 10 11 12 13 14 15 16
Preliminary Technical Data
29 30 31 32 COMR COMR INLB INHB Paddle Common for difference output and Temp Sensor Common for difference output and Temp Sensor AC coupled RF common for Channel B AC coupled RF input for Channel B Internally connected to COMR
ADL5519
Rev. PrB | Page 11 of 27
ADL5519 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
VP = 5 V; TA = +25C, -40C, +85C; CLPA/B = OPEN. Colors: +25C black, -40C blue, +85C red.
Figure 3: OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive,
Figure 6: OUT[P, N]Gain and Log Conformance vs. Input Amplitude at 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive (Note that the OUTP and OUTN Error Curves Overlap)
Figure 4: Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive
Figure 7: Distribution of [OUTP - OUTN] Gain and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
Figure 5: Distribution of [OUTA - OUTB] Gain vs. Input Amplitude over Temperature for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive
Figure 8: OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive,
Rev. PrB | Page 12 of 27
Preliminary Technical Data THEORY OF OPERATION
The ADL5519 is a dual-channel 6-stage demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. Sharing much of its design with the AD8317 logarithmic detector/controller, the ADL5519 maintains tight intercept variability vs. temperature over a 50 dB range. Each measurement channel offers equivalent performance to the AD8317. The complete circuit block diagram is shown in Figure 9.
COMR COMR VPSA TEMP VPSR ADJA CLPA VSTA
ADL5519
24
23
22
21
20
19
18
17
TEMP INHA 25 INLA 26 COMR 27 PWDN 28 COMR 29 COMR 30 INLB 31 INHB 32 BIAS
1 2 3 4 5 6 7 8 25 26 27 28
The maximum input with 1 dB log-conformance error is typically 0 dBm (re: 50 ). The noise spectral density referred to the input is 1.15 nV/Hz, which is equivalent to a voltage of 118 V rms in a 10.5 GHz bandwidth or a noise power of -66 dBm (re: 50 ). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the ADL5519 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMR, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMR pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB. The logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, please refer to the AD8307 data sheet, available at www.analog.com.) The cells have a nominal voltage gain of 9 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high, due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a squarelaw detector cell is used to rectify the signal. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. Along with the six gain stages and detector cells, an additional detector is included at the input of each measurement channel,, providing a 50 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node: ID x log10(VIN/VINTERCEPT) where:
NC OUTA FBKA OUTP OUTN FBKB OUTB NC
CHANNEL A Log Detector
OUTA OUTB
29 30
CHANNEL B Log Detector
31 32
COMR
COMR
VPSB
Figure 9. Block Diagram
Each measurement channel is a fully differential design and uses a proprietary, high speed SiGe process, extending high frequency performance. Figure 10 shows the basic diagram of the ADL5519's channel A signal path, the functionality is identical for channel B.
V I VSTA
CLPB
ADJB
VREF
VSTB
VLVL
I DET INHA INLA DET DET DET
V
OUTA
CLPA
ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V).
Figure 10. Single Channel Block Diagram
Rev. PrB | Page 13 of 27
ADL5519 USING THE ADL5519
BASIC CONNECTIONS
The ADL5519 is specified for operation up to 10 GHz; as a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage of between 3.0 V and 5.5 V should be applied to VPSA, VPSB, and VPSR. Power supply decoupling capacitors of 100 pF and 0.1 F should be connected close to these power supply pins.
VPSR
Preliminary Technical Data
VPSA 5pF 5pF
CURRENT
18.7k INHA
18.7k
FIRST GAIN STAGE 2k A = 9dB
INLA Gm STAGE OFFSET COMP
Figure 12. Single Channel Input Interface
R4 0 VPSA C12 0.1F R3 0 C7 100pF SEE TEXT C15 0.1F C8 100pF SEE TEXT SEE TEXT OUTPUT VOLTAGE B
18 17
24
23
22
21
20
19
C4 47nF
INHA 25
COMR COMR VPSA INHA
ADJA
VPSR
TEMP CLPA
VSTA NC 16
R8 0 R21 0
R5 52.3
26
INLA
OUTA 15
While the input can be reactively matched, in general this is not necessary. An external 52.3 shunt resistor (connected on the signal side of the input coupling capacitors, as shown in Figure 11) combines with the relatively high input impedance to give an adequate broadband 50 match. The coupling time constant, 50 x CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(2 x 50 x CC ), where C1 = C2 = CC. Using the typical value of 47 nF, this high pass corner will be ~68 kHz. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency.
C3 47nF
27
SETPOINT VOLTAGE B
COMR
FBKA 14
R9 0 R1 1k
ADL5519ACPZ
28
PWDN
OUTP 13
DIFF OUT +
29
COMR EXPOSED PADDLE
OUTN 12 R10 0 R2 1k
DIFF OUT -
30
COMR
FBKB 11
C2
31
INLB
OUTB 10
R20 0
R6 52.3
INHB
47nF
32
OUTPUT VOLTAGE B
INHB COMR COMR VPSB
1 2 3
NC 9 ADJB
4
C1 47nF
VREF
5
VLVL
6
CLPB
7
VSTB
8
R12 0
C11 100pF
SEE TEXT R11 0
R7 0
SEE TEXT
SETPOINT VOLTAGE B
C16 0.1F VPSB
Figure 11. Basic Connections
The paddle of the LFCSP_VD package is internally connected to COMR. For optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane.
TEMPERATURE SENSOR INTERFACE
The ADL5519 provides a temperature sensor output capable of driving about 1.6 mA. The temperature scaling factor of the output voltage is approximately 2 mV/C. The typical absolute voltage at 25C is ~620 mV.
VPSR INTERNAL VPTAT TEMP 12k
INPUT SIGNAL COUPLING
The RF inputs (INHA and INHB) are single-ended and must be ac-coupled. INLA and INLB (input common) should be ac-coupled to ground. Suggested coupling capacitors are 47 nF ceramic 0402-style capacitors for input frequencies of 1 MHz to 10 GHz. The coupling capacitors should be mounted close to the INHA[INHB] and INLA[INLB} pins. The coupling capacitor values can be increased to lower the input stage's high-pass cutoff frequency. The high-pass corner is set by the input coupling capacitors and the internal 10 pF high-pass capacitor. The dc voltage on INHA[INHB] and INLA[INLB] is about one diode voltage drop below the supply voltage.
4k
COMR
Figure 13. TEMP Interface Simplified Schematic
Rev. PrB | Page 14 of 27
Preliminary Technical Data
POWER-DOWN INTERFACE
The operating and stand-by currents for the ADL5519 at 25C are approximately 65 mA and 1 mA, respectively. The PWDN and ADJ[A,B] pins are connected to the base of and NPN transistor to force a power down condition. Typically, when PWDN is pulled >2.5 V, the ADL5519 is powered down from 65mA to <1mA. The output reaches to within 0.1 dB of its steady-state value in about 1.6 s; the reference voltage is available to full accuracy in a much shorter time. This wake-up response time varies depending on the input coupling network and the capacitance at pins CLP[A, B]. The individual log channels can be disabled by installing a 0 pull up resistor from ADJ[A,B] to VPS[A,B].
CLP[A,B] OUT[A, B] 1.2k VPS[A, B]
ADL5519
400
COMR
Figure 15. OUT[A, B] Interface Simplified Schematic
OUT[A, B] can source and sink up to 2.2 mA.
DIFFERENCE OUTPUT, OUT[P, N]
The ADL5519 incorporates two operational amplifiers with rail-to-rail output capability to provide a channel difference output.
VLVL 1k OUTA OUTB 1k 1k FBKA VLVL 1k OUTB OUTA 1k 1k FBKB COMR OUTN
05334-030
SETPOINT INTERFACE, VST[A, B]
The VSET input drives the high impedance (20 k) input of an internal op amp. The VSET voltage appears across the internal 1.5 k resistor to generate ISET. When a portion of VOUT is applied to VSET, the feedback loop forces -ID x log10(VIN/VINTERCEPT) = ISET. If VSET = VOUT/2x, then ISET = VOUT/(2x x 1.5 k). The result is VOUT = (-ID x 1.5 k x 2x) x log10(VIN/VINTERCEPT)
ISET
VPSR
1k OUTP
COMR VPSR
1k
20k VSET
VSET
Figure 16. OUT[P, N] Interface Simplified Schematic
20k 1.5k COMM COMM
05541-025
Figure 14. VST[A, B] Interface Simplified Schematic
The slope is given by -ID x 2x x 1.5 k = -22 mV/dB x x. For example, if a resistor divider to ground is used to generate a VSET voltage of VOUT/2, then x = 2. The slope is set to -880 V/decade or -44 mV/dB.
As in the case of the output drivers for OUT[A, B], the output stages have the capability of driving 2.2 mA. OUTA and OUTB are internally connected through 1 k resistors to the inputs of each op amp. The pin VLVL is connected to the positive terminal of both op amps through 1 k resistors to provide level shifting. The negative feedback terminal is also made available through a 1 k resistor. The input impedance of VLVL is 1 k and FBK[A, B] is 2 k. See Figure 17 for the connections of these pins.
27 28
FBKA OUTP OUTN FBKB
OUTPUT INTERFACE, OUT[A, B]
The OUT[A,B] pin is driven by a PNP output stage. An internal 10 resistor is placed in series with the output and the OUT[A,B] pin. The rise time of the output is limited mainly by the slew on CLP[A,B]. The fall time is an RClimited slew given by the load capacitance and the pulldown resistance at OUT[A,B]. There is an internal pulldown resistor of 1.6 k. A resistive load at OUT[A,B] is placed in parallel with the internal pull-down resistor to provide additional discharge current.
OUTA OUTB
29 30
Figure 17. Op Amp Connections (All Resistors are 1 k 20%)
If OUTP is connected to FBKA, then OUTP is given as OUTP = OUTA - OUTB + VLVL (9)
If OUTN is connected to FBKB, then OUTN is given as OUTN = OUTB - OUTA + VLVL
Rev. PrB | Page 15 of 27
(10)
ADL5519
In this configuration, all four measurements, OUT[A, B, P, N], are made available simultaneously. A differential output can be taken from OUTP - OUTN, and VLVL can be used to adjust the common-mode level for an ADC connection.
Preliminary Technical Data
The slope is very stable vs. process and temperature variation. When base-10 logarithms are used, VSLOPE/DECADE represents the volts/decade. A decade corresponds to 20 dB; VSLOPE/DECADE/20 = VSLOPE/dB represents the slope in volts/dB. As noted in Equation 1 and Equation 2, the VOUT voltage has a negative slope. This is also the correct slope polarity to control the gain of many power amplifiers in a negative feedback configuration. Because both the slope and intercept vary slightly with frequency, it is recommended to refer to the Specifications section for application-specific values for slope and intercept. Although demodulating log amps respond to input signal voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. In this case, the characteristic impedance of the system, Z0, must be known to convert voltages to their corresponding power levels. The following equations are used to perform this conversion: P(dBm) = 10 x log10(Vrms2/(Z0 x 1 mW)) P(dBV) = 20 x log10(Vrms/1 Vrms) P(dBm) = P(dBV) - 10 x log10(Z0 x 1 mW/1 Vrms2) (3) (4) (5)
MEASUREMENT MODE
The ADL5519 requires a single supply of 3.0 V to 5 V. The supply is connected to the three supply pins, VPSA, VPSB, and VPSR. Each pin should be decoupled using the two capacitors with values equal or similar to those shown in Figure 19. These capacitors must provide a low impedance over the full frequency range of the input, and they should be placed as close as possible to the positive supply pins. Two different capacitors are used in parallel to provide a broadband ac short to ground. The device is placed in measurement mode by connecting OUTA and/or OUTB to VSTA and/or VSTB, respectively. As seen in Figure 18, the ADL5519 has an offset voltage, a negative slope, and a VOUT[A,B] measurement intercept at the high end of its input signal range.
For example, PINTERCEPT for a sinusoidal input signal expressed in terms of dBm (decibels referred to 1 mW), in a 50 system is PINTERCEPT(dBm) = PINTERCEPT (dBV) - 10 x log10(Z0 x 1 mW/1 Vrms2) = +2 dBV - 10 x log10(50x10-3) = +15 dBm For a square wave input signal in a 200 system, PINTERCEPT = -1 dBV - 10 x log10[(200 x 1 mW/1Vrms2)] = +6 dBm
Figure 18. Typical Output Voltage vs. Input Signal, Single Channel
(6)
The output voltage vs. input signal voltage of the ADL5519 is linear-in-dB over a multidecade range. The equation for this function is of the form VOUT = X x VSLOPE/DEC x log10(VIN/VINTERCEPT) = X x VSLOPE/dB x 20 x log10(VIN/VINTERCEPT) where: X is the feedback factor in VSET = VOUT/X. VSLOPE/DEC is nominally -440 mV/decade or -22 mV/dB. VINTERCEPT is the x-axis intercept of the linear-in-dB portion of the VOUT vs. VIN curve (Figure 18). VINTERCEPT is +2 dBV for a sinusoidal input signal. An offset voltage, VOFFSET, of 0.35 V is internally added to the detector signal, so that the minimum value for VOUT is X x VOFFSET. So for X = 1, minimum VOUT is 0.35 V. (1) (2)
Further information on the intercept variation dependence upon waveform can be found in the AD8313 and AD8307 data sheets. As the input signal to Channel A and Channel B are swept over their nominal input dynamic range of +10 dBm to -50 dBm, the output swings from 0.5 V to 1.75 V. The voltages OUTA and OUTB are also internally applied to a difference amplifier with a gain of two. So as the dB difference between INA and INB ranges from approximately -30 dB to +30 dB, the difference voltage on OUTP and OUTN swings from 0.5 V to 1.75 V. Input differences larger than 30 dB can be measured as long as the absolute input level at INA and INB are within their nominal ranges of +10 dBm to -50 dBm. However, measurement of large differences between INA and INB are affected by on-chip signal leakage. The common-mode level of OUTP and OUTN is set by the voltage applied to VLVL. These output can be easily biased up to a common-mode voltage of 2.5 V by connecting VREF to VLVL. As the gain range is swept, OUTP swings from approximately 0.5 V to 1.75 V and OUTN swings from 1.75 V to 0.5 V.
Rev. PrB | Page 16 of 27
Preliminary Technical Data
VPSR
ADL5519
R4 0 VPSA C12 0.1F R3 0 C7 100pF SEE TEXT
C15 0.1F C8 100pF SEE TEXT SEE TEXT OUTPUT VOLTAGE B
18 17
24
23
22
21
20
19
C4 47nF
INHA 25
COMR COMR VPSA INHA
ADJA
VPSR
TEMP
CLPA
VSTA NC 16
R8 0 R21 0
R5 52.3
26
INLA
OUTA 15
C3 47nF
27
SETPOINT VOLTAGE B
COMR
FBKA 14
R9 0 R1 1k
ADL5519ACPZ
28
PWDN
OUTP 13
DIFF OUT +
29
COMR EXPOSED PADDLE
OUTN 12 R10 0 R2 1k
DIFF OUT -
30
COMR
FBKB 11
C2
31
INLB
OUTB 10
R20 0
R6 52.3
INHB
47nF
32
OUTPUT VOLTAGE B
INHB COMR COMR VPSB
1 2 3
NC 9 ADJB
4
C1 47nF
VREF
5
VLVL
6
CLPB
7
VSTB
8
R12 0
C11 100pF
SEE TEXT R11 0
R7 0
SEE TEXT
SETPOINT VOLTAGE B
C16 0.1F VPSB
Figure 19. Basic Connections for Operation in Measurement Mode
CONTROLLER MODE
In addition to being a measurement device, the ADL5519 can also be configured to measure and control signal levels. The ADL5519 has two controller modes. Each of the two log detectors can be separately configured to set and control the output power level of a variable gain amplifier (VGA) or variable voltage attenuator (VVA). Alternatively, the two log detectors can be configured to measure and control the gain of an amplifier or signal chain. The channel difference outputs can be used for controlling a feedback loop to the ADL5519's RF inputs. A capacitor connected between FBKA and OUTP forms an integrator, keeping in mind that the on-chip 1 k feedback resistor forms a zero. (The value of the on-chip resistors can vary as much as 20% with manufacturing process variation.) If Channel A is driven and Channel B has a feedback loop from OUTP through a PA, then OUTP integrates to a voltage value such that OUTB = (OUTA + VLVL)/2 (11)
OUTN = 0 V For VLVL < OUTA/3, Otherwise, OUTN = (3 x VLVL - OUTA)/2
(12)
(13)
If VLVL is connected to OUTA, then OUTB is forced to equal OUTA through the feedback loop. This flexibility provides the user with the capability to measure one channel operating at a given power level and frequency while forcing the other channel to a desired power level at another frequency. ADJA and ADJB should be set to different voltage levels to reduce the temperature drift of the output measurement. The temperature drift will be statistical sum of the drift from Channel A and Channel B. As stated before, VLVL can be used to force the slaved channel to operate at a different power than the other channel. If the two channels are forced to operate at different power levels, then some static offset occurs due to voltage drops across metal wiring in the IC. If an inversion is necessary in the feedback loop, OUTN can be used as the integrator by placing a capacitor between OUTN
The output value from OUTN may or may not be useful. It is given by
Rev. PrB | Page 17 of 27
ADL5519
and OUTP. This changes the output equation for OUTB and OUTP to OUTB = 2 x OUTA - VLVL For VLVL < OUTA/2, OUTN = 0 V Otherwise, OUTN = 2 x VLVL - OUTA (16) (15) (14)
Preliminary Technical Data
CLPA should be chosen to provide stable loop operation for the complete output power control range. If the slope (in dB/V) of the gain control transfer function of the VGA is not constant, CLPA must be chosen to guarantee a stable loop when the gain control slope is at its maximum. On the other hand, CLPA must provide adequate averaging to the internal low range squaring detector so that the rms computation is valid. Larger values of CLPA tend to make the loop less responsive. The relationship between VSTA and the RF input follows from the measurement mode behavior of the device. For example, from Figure 8, which shows the measurement mode transfer function at 880 MHz, it can be seen that an input power of -10 dBm yields an output voltage of 2.5 V. Therefore, in controller mode, VSTA should be set to 2.5 V, which results in an input power of -10 dBm to the ADL5519.
The previous equations are valid when Channel A is driven and Channel B is slaved through a feedback loop. When Channel B is driven and Channel A is slaved, the above equations can be altered by changing OUTB to OUTA and OUTN to OUTP.
Automatic Power Control
Figure 20 shows how the device should be reconfigured to control output power.
PIN VGA OR VVA (OUTPUT POWER INCREASES AS VAPC DECREASES) VAPC ATTENUATOR (0V TO 4.9V AVAILABLE SWING) OUTA 0.1F INHA
POUT
The RF input to the device is configured as before. A directional coupler taps off some of the power being generated by the VGA (typically a 10 dB to 20 dB coupler is used). A power splitter can be used instead of a directional coupler if there are no concerns about reflected energy from the next stage in the signal chain. Some additional attenuation may be required to set the maximum input signal at the ADL5519 to be equal to the recommended maximum input level for optimum linearity and temperature stability at the frequency of operation. VSTA and OUTA are no longer shorted together. OUTA now provides a bias or gain control voltage to the VGA. The gain control sense of the VGA must be positive and monotonic, that is, increasing voltage tends to increase gain. However, the gain control transfer function of the device does not need to be well controlled or particularly linear. If the gain control sense of the VGA is negative, an inverting op amp circuit with a dc offset shift can be used between the ADL5519 and the VGA to keep the gain control voltage in the 0 V to 5 V range. VSTA becomes the setpoint input to the system. This can be driven by a DAC, as shown in Figure 20, if the output power is expected to vary, or it can simply be driven by a stable reference voltage if constant output power is required. This DAC should have an output swing that covers the 0 V to 3.5 V range. The AD7391 and AD7393 serial-input and parallel-input 10-bit DACs provide adequate resolution (4 mV/bit) and an output swing up to 4.5 V. When VSTA is set to a particular value, the ADL5519 compares this value to the equivalent input power present at the RF input. If these two values do not match, OUTA increases or decreases in an effort to balance the system. The dominant pole of the error amplifier/integrator circuit that drives OUTA is set by the capacitance on Pin CLPA; some experimentation may be necessary to choose the right value for this capacitor. In general,
ADL5519
INLA 0.1F VSTA CLPA SEE TEXT DAC 0V TO 3.5V
50
Figure 20. Operation in Controller Mode for Automatic Power Control
Automatic Gain Control
Figure 21 shows how the ADL5519 can be connected to provide automatic gain control to an amplifier or signal chain. Additional pins are omitted for clarity. In this configuration, both log detectors are connected in measurement mode with appropriate filtering being used on CLP[A, B]. OUTA, however, is also connected to the VLVL pin of the on-board difference amplifier. Also, the OUTP output of the difference amplifier drives a variable gain element (either VVA or VGA) and is connected back to the FBKA input via a capacitor so that it is operating as an integrator. Assume that OUTA is much bigger than OUTB. Because OUTA also drives VLVL, this voltage is also present on the noninverting input of the op amp driving OUTP. This results in a net current flow from OUTP through the integrating capacitor into the FBKA input. This results in the voltage on OUTP decreasing. If the gain control transfer function of the VVA/VGA is negative, this increases the gain, which in turn increases the input signal to INHB. The output voltage on the integrator continues to
Rev. PrB | Page 18 of 27
Preliminary Technical Data
increase until the power on the two input channels is equal, resulting in a signal chain gain of unity. If a gain other than 0 dB is required, an attenuator can be used in one of the RF paths, as shown in Figure 21. Alternatively, power splitters or directional couplers of different coupling factors can be used. Another convenient option is to apply a voltage on VLVL other than OUTA. Refer to Equation 11 and the Controller Mode section for more detail.
DIRECTIONAL OR POWER SPLITTER
ADL5519
If the VGA/VVA has a positive gain control sense, the OUTN output of the difference amplifier can be used with the integrating capacitor tied back to FBKB. The choice of the integrating capacitor affects the response time of the AGC loop. Small values give a faster response time but can result in instability, whereas larger values reduce the response time. Note that in this mode, the capacitors on CLPA and CLPB, which perform the rms averaging function, must still be used and also affect the loop response time.
VGA/VVA DIRECTIONAL OR POWER SPLITTER
CLPA
ADL5519
0.1F INHA 50 0.1F OUTP DIFF OUT + OUTN 0.1F 50 0.1F VSTB INLB INHB CHANNEL B Log Detector FBKB OUTB INLA CHANNEL A Log Detector VSTA OUTA FBKA CINT ATTENUATOR
VLVL
CLPB
Figure 21. Operation in Controller Mode for Automatic Gain Control
Rev. PrB | Page 19 of 27
Preliminary Technical Data
TEMPERATURE COMPENSATION ADJUSTMENT
The ADL5519 has a highly stable measurement output with respect to temperature. However, when the RF inputs exceed a frequency of 600 MHz, the output temperature drift must be compensated for using ADJ[A, B] for optimal performance. Proprietary techniques are used to compensate for the temperature drift. The absolute value of compensation varies with frequency and circuit board material. Table 4 shows recommended voltages for ADJ[A, B] to maintain a temperature drift error of typically 0.5 dB or better over the entire rated temperature range with the recommended baluns. Table 4: Recommended ADJ[A,B] Voltage Levels
Frequency 50 MHz 100 MHz 900 MHz 1.8 GHz 1.9 GHz 2.2 GHz 3.6 GHz 5.3 GHZ 5.8 GHz 8 GHz Recommended ADJ[A,B] Voltage TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
VREF ADL5519 VTADJ ADJ[A,B]
ADL5519
ICOMP
COMR
COMR
Figure 23. ADJ[A, B] Interface Simplified Schematic
DEVICE CALIBRATION AND ERROR CALCULATION
The measured transfer function of the ADL5519 at 2.14 GHz is shown in Figure 24. The figure shows plots of both output voltage vs. input power and calculated error vs. input power. As the input power varies from -50 dBm to 0 dBm, the output voltage varies from 0.4 V to about 2.8 V.
Compensating the device for temperature drift using ADJ[A, B] allows for great flexibility. If the user requires minimum temperature drift at a given input power or subset of the dynamic range, the ADJ[A, B] voltage can be swept while monitoring OUT[A, B] over temperature. Figure 22 shows the result of such an exercise. The value of ADJ[A, B] where the output has minimum movement (approximately 0.77 V for the example in Figure 22) is the recommended voltage for ADJ[A, B] to achieve minimum temperature drift at a given power and frequency.
Figure 24. Transfer Function at 2.14 GHz.
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. The equation for output voltage can be written as VOUT = Slope x (PIN - Intercept) Where Slope is the change in output voltage divided by the change in power (dB), and Intercept is the calculated power at which the output voltage would be 0 V. (Note that Intercept is a theoretical value; the output voltage can never achieve 0 V). In general, the calibration is performed by applying two known signal levels to the ADL5519's input and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear-in-dB operating range of the device (see the Specifications section for more details).
Figure 22. OUTA vs. ADJA over Temp. Pin = -30 dBm, 1.9 GHz
The ADJ[A, B] input has high input impedance. The input can be conveniently driven from an attenuated value of VREF using a resistor divider, if desired. Figure 23 shows a simplified schematic representation of the ADJ[A, B] interface.
Calculation of the slope and intercept is done using the equations: Slope = (VOUT1 - VOUT2)/(PIN1 - PIN2) Intercept = PIN1 - (VOUT1/Slope)
Rev. PrB | Page 20 of 27
Preliminary Technical Data
Once slope and intercept have been calculated, an equation can be written that will allow calculation of the input power based on the output voltage of the detector. PIN (unknown) = (VOUT1(measured)/Slope) + Intercept The log conformance error of the calculated power is given by Error (dB) = (VOUT(MEASURED) - VOUT(IDEAL))/Slope Figure 24 includes a plot of the error at 25C, the temperature at which the log amp is calibrated. Note that the error is not zero. This is because the log amp does not perfectly follow the ideal VOUT vs. PIN equation, even within its operating region. The error at the calibration points (-43 dBm and -23 dBm in this case) will, however, be equal to zero by definition. Figure 24 also includes error plots for the output voltage at -40C and +85 C. These error plots are calculated using the slope and intercept at 25C. This is consistent with calibration in a mass-production environment, where calibration at temperature is not practical.
Figure 25. External Network to Raise Slope
ADL5519
ADL5519
OUT[A,B] R1 VST[A,B] R2 VOUT
OUTPUT FILTERING
Accurate power detection for signals with RF bursts is achieved when the ADL5519 is able to respond quickly to the change in RF power. For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the CLP[A,B] pin be left unconnected and free of any stray capacitance. The nominal output video bandwidth of 50 MHz can be reduced by connecting a ground-referenced capacitor (CFLT) to the CLPF pin, as shown in Figure 26. This is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals).
ADL5519
ILOG[A,B] +4 1.5k 3.5pF OUT[A,B]
ALTERING THE SLOPE
None of the changes to operating conditions discussed so far affect the logarithmic slope, VSLOPE, in Equation 7. The slope can readily be altered by controlling the fraction of OUT[A, B] that is fed back to the setpoint interface at the VST[A, B] pin. When the full signal from OUT[A, B] is applied to VST[A, B], the slope assumes its nominal value of -22 mV/dB. It can be increased by including a voltage divider between these pins, as shown in Figure 25. Moderately low resistance values should be used to minimize scaling errors due to the approximately 40 k input resistance at the VST[A, B] pin. Keep in mind that this resistor string also loads the output, and it eventually reduces the load-driving capabilities if very low values are used. Equation 17 can be used to calculate the resistor values. R1 = R2' (SD/-22 - 1) where: SD is the desired slope, expressed in mV/dB. R2' is the value of R2 in parallel with 40 k. For example, using R1 = 1.65 k and R2 = 1.69 k (R2' = 1.62 k), the nominal slope is increased to -44 mV/dB. Operating at a high slope is useful when it is desired to measure a particular section of the input range in greater detail. When the slope is raised by some factor, the loop capacitor, CLP[A, B], should be raised by the same factor to ensure stability and to preserve a chosen averaging time. The slope can be lowered by placing a voltage divider after the output pin, following standard practice. (17)
CLP[A,B] CFLT
Figure 26. Lowering the Postdemodulation Bandwidth
CFLT is selected using the following equation:
C FLT =
( x 1.5 k x Video Bandwidth )
1
- 3.5 pF (10)
The video bandwidth should typically be set to a frequency equal to about one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered.
BASIS FOR ERROR CALCULATIONS
The slope and intercept are derived using the coefficients of a linear regression performed on data collected in its central operating range. Error is stated in two forms: (1) error from linear response to CW waveform and (2) output delta from 25C performance. The error from linear response to CW waveform is the decibel difference in output from the ideal output defined by the conversions gain and output reference. This is a measure of the linearity of the device response to both CW and modulated waveforms. The error in dB is calculated by
Rev. PrB | Page 21 of 27
ADL5519
Error (dB) =
VOUT - Slope x (PIN - PZ ) Slope
Preliminary Technical Data
slope and intercept of each device. However, it verifies the linearity and the effect of modulation on the device's response. Similarly, error from 25C performance uses the 25C performance of a given device and waveform type as the reference from which all other performance parameters shown alongside it are compared. It is predominantly (and most often) used as a measurement of output variation with temperature.
where PZ is the x-axis intercept expressed in dBm. This is analogous to the input amplitude that would produce an output of 0 V, if such an output was possible. Error from the linear response to the CW waveform is not a measure of absolute accuracy, since it is calculated using the
Rev. PrB | Page 22 of 27
Preliminary Technical Data EVALUATION BOARD
Table 5. Evaluation Board (Rev. A) Configuration Options
Component VPOS, GND1, GND2, GND3 R5, R6, C1, C2, C3, C4 Function Supply and Ground Connections. GND1, GND2, GND3 are internally connected together. Input Interface. The 52.3 resistor in positions R5 and R6 combine with the ADL5519's internal input impedance to give a broadband input impedance of about 50 . Capacitors C1, C2, C3, and C4 are dc-blocking capacitors. A reactive impedance match can be implemented by replacing R5[R6] with an inductor and C1[C3] and C2[C4] with appropriately valued capacitors. Temperature Sensor Interface: The temperature sensor output voltage is available at the test point labeled TEMP. Temperature Compensation Interface. The internal temperature compensation network is optimized for input signals up to TBD GHz when the voltage applied to the ADJ[A,B] pin is TBD V. This circuit can be adjusted to optimize performance for other input frequencies by changing the value of this voltage. See Table 4 for specific voltage levels. The pads for R27/R28 or R27/R29 can be used for voltage dividers to set the ADJ[A,B] voltages for temperature compensation at different frequencies. The individual log channels can be disabled by installing 0 resistors in positions R18 and R19 Output Interface--Measurement Mode. In measurement mode, a portion of the output voltage is fed back to Pin VSTA[VSTB] via R8[R12]. The magnitude of the slope of the OUTA[OUTB] output voltage response can be increased by reducing the portion of VOUTA [VOUTB]that is fed back to VSTA[VSTB]. R20[R21} can be used as a backterminating resistor or as part of a single-pole, low-pass filter. Default Conditions Not applicable R5 = 52.3 (Size 0402) C1 = 47 nF (Size 0402) C2 = 47 nF (Size 0402) R6 = 52.3 (Size 0402) C3 = 47 nF (Size 0402) C4 = 47 nF (Size 0402) R14 = 0 (Size 0603)
ADL5519
R14
R13, R17, R18, R19, R27, R28, R29
R13 = open (size 0603) R17 = open (size 0603) R18 = 0 (size 0603) R19 = 0 (size 0603) R27 = 0 (size 0603) R28 = open (size 0603) R29 = open (size 0603) R8 = 0 (Size 0603) R12 = 0 (Size 0603) R15 = open (Size 0603) R16 = open (Size 0603) R20 = 0 (Size 0603) R21 = 0 (Size 0603) R22 = open (Size 0603) R23 = open (Size 0603) C13 = open (Size 0603) C14 = open (Size 0603) R8 = 0 (Size 0603) R12 = 0 (Size 0603) R22 = open (Size 0603) R23 = open (Size 0603)
R8, R12, R15, R16, R20, R21, R22, R23, C13, C14
R8, R12, R22, R23
R3, R4, R11, C7, C8 C11, C12, C15, C16
Output Interface--Controller Mode. In this mode, R8[R12] must be open. In controller mode, the ADL5519 can control the gain of an external component. A setpoint voltage is applied to Pin VSTA[VSTB], the value of which corresponds to the desired RF input signal level applied to the corresponding ADL5519 RF input. A sample of the RF output signal from this variable-gain component is selected, typically via a directional coupler, and applied to ADL5519 RF input. The voltage at Pin OUTA[OUTB] is applied to the gain control of the variable gain element. A control voltage is applied to Pin VSTA[VSTB]. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising R8[R12] and R22[R23], or a capacitor can be installed in position R22[R23] to form a low-pass filter along with R8[R12]. Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the ADL5519 and a 0.1 F capacitor placed nearer to each power supply input pin.
R3 = 0 (Size 0603) R4 = 0 (Size 0603) R11 = 0 (Size 0603) C7 = 100 pF (Size 0603) C8 = 100 pF (Size 0603) C11 = 100 pF (Size 0603) C12 = 0.1 F (Size 0603) C15 = 0.1 F (Size 0603) C16 = 0.1 F (Size 0603)
Rev. PrB | Page 23 of 27
ADL5519
R1, R2, R9, R10 Output Interface - Difference
Preliminary Technical Data
R1 = 1K (Size 0603) R2 = 1K (Size 0603) R9 = open (Size 0603) R10 = open (Size 0603) C9 = 100 pF (Size 0603) C10 = 100 pF (Size 0603)
C9, C10
Filter Capacitor. The low-pass corner frequency of the circuit that drives Pin OUTA[OUTB] can be lowered by placing a capacitor between CLPA[CLPB] and ground. Increasing this capacitor increases the overall rise/fall time of the ADL5519 for pulsed input signals. See the Output Filtering section for more details.
Rev. PrB | Page 24 of 27
Preliminary Technical Data
VPSR
ADL5519
ADJA R3 0 C7 100pF
R4 0
C15 0.1F C8 100pF
VPSA C12 0.1F
C9 100pF
R13 OPEN R18 OPEN R14 OPEN
TEMP SENSOR R23 OPEN
19 18 17
OUTPUT VOLTAGE B
24
23
22
21
20
C4 47nF
INHA
COMR COMR VPSA
25 INHA
ADJA
VPSR
TEMP CLPA
VSTA NC 16
R8 0 R21 0 R15 OPEN C13 OPEN SETPOINT VOLTAGE B
R5 52.3
26 INLA
OUTA 15
C3 47nF
27 COMR
R9 FBKA 14 0
ADL5519ACPZ
PWDN 28 PWDN
OUTP 13
R1 1k
DIFF OUT +
29 COMR
OUTN 12 EXPOSED PADDLE R10 0 R2 1k
DIFF OUT -
30 COMR
FBKB 11
C2
31 INLB
OUTB 10
R20 0 R16 OPEN C14 OPEN
R6 52.3
INHB
47nF
32 INHB
OUTPUT VOLTAGE B
NC 9 ADJB
4
C1 47nF
COMR COMR VPSB
1 2 3
VREF
5
VLVL
6
CLPB
7
VSTB
8
R12 0
ADJA R29 OPEN
ADJB R28 OPEN R27 0 VREF C16 100pF C11 0.1F
R19 OPEN R11 0
C5 0.1F R17 OPEN R7 0 C6 OPEN
C10 100pF
R22 OPEN
SETPOINT VOLTAGE B
VPOS R24 GND1 GND2 GND3 0 R25 0 R26 0 VPSR VPSB VPSA
VPSB
ADJB
VREF
VLVL
Figure 27. Evaluation Board Schematic
Rev. PrB | Page 25 of 27
Preliminary Technical Data
ADL5519
Figure 28. Top Side Layout
Figure 30: Bottom Side Layout
Figure 29. Top Side Silkscreen Figure 31: Bottom Side Silkscreen
Rev. PrB | Page 26 of 27
Preliminary Technical Data OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX
25 24 PIN 1 INDICATOR 32 1
ADL5519
0.60 MAX PIN 1 INDICATOR 2.85 2.70 SQ 2.55
98
TOP VIEW
4.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
17 16
0.20 MIN 3.50 REF
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 0.20 REF COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_VD] 5 mm x 5 mm Body, Very Thin, Dual Lead (CP-32-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5519ACPZ-R7 1 ADL5519ACPZ-R21 ADL5519ACPZ-WP1, 2 ADL5519-EVALZ1
1 2
Temperature Package -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead LFCSP_VD 32-Lead LFCSP_VD 32-Lead LFCSP_VD Evaluation Board
Package Option CP-32-8 CP-32-8 CP-32-8
Branding TBD TBD TBD
Z = Pb-free part. WP = waffle pack.
Rev. PrB | Page 27 of 27

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